This introductory session delves into the heightened scrutiny required for SI/PI design, simulation, and implementation in our newest systems. It highlights the complexities faced in our High-Speed Serdes design at 56-224 Gbps, addresses critical issues in DDR5 for 6400/8400MTs implementation, and explores difficulties in distributing 1-2kW of power to our latest ICs.  Highlighting these challenges and potential solutions establishes the foundation for the exciting content of the SI-PI Global University

Stephen Scearce is a Hardware Engineering Director of Cisco/Meraki’s Electronics Packaging and Diagnostics team.  Stephen provides the technical direction/leadership for Signal Integrity, Power Integrity, Mechanical/Thermal Design, ECAD, and Software Diagnostics design in US/China.  Stephen has worked for Cisco for 24 years focused on ASIC/System PI, SI, Package Design, and EMC design.  He holds 13 issued patents and has co-authored 17 papers.   He has volunteered for the IEEE Electromagnetic Compatibility Society for the past 11 years and is currently serving as the Society Treasurer (2023-2026), and the 2025 EMC+SIPI Symposium Vice Chair. Stephen received his BSET and MSEE from Old Dominion University, Norfolk VA.

In this session we will discuss signal integrity effects and design considerations of passive interconnects.  Understanding the effects channels have on signals is critical to designing for signal integrity, and designing for signal integrity is critical for product design.  Concepts including lumped and transmission line effects, reflections, and terminations will be presented and illustrated with examples.  A grasp of these fundamental concepts enables engineers to solve many signal integrity challenges and is a foundation for learning additional, and more advanced topics in signal integrity.

John Golding is a Senior Applications Engineer Consultant with Siemens EDA. He has been working with engineers in several industries for over 10 years to solve their Signal and Power Integrity analysis challenges. Prior to his current role, he was a hardware engineer for 18 years where he responsible for the design, analysis, and verification of high-speed communications products. He holds a BSEE degree from the University of Michigan and a MSEE degree from Illinois Tech.

The latest trends in SI design require an understanding from basic interconnect design challenges through to how the DSP receivers correct interconnect distortions. PCB stackup design choices have tradeoffs that impact loss, routing density, and vertical transitions. These vertical transitions, especially, have negative impacts on the breakout region (BOR) connector performance targets that go along with mechanical requirements for mating of the connector. However, signaling is ultimately in the time domain, and it can be helpful to use single bit responses of the channel to understand the limits of equalization on ISI. Additionally, modulation choices such as Pulse Amplitude (PAM4 or PAM6) tighten the requirements on SNR. The presentation introduces the above subjects, and it shares tips specific to the design of interconnect component evaluation for 224 Gb/s signaling.

Brandon T. Gore is presently a Principal Technologist at Samtec managing both the Signal Integrity R&D and Electronic Industry Standards teams. His research focuses are advanced interconnect materials, glass packaging, direct drive optics, and general signal integrity bottlenecks for beyond 200Gbps data rates. He is an active contributor to both IEEE 802.3 and OIF Common Electrical I/O projects. Brandon received the PhD degree in electrical engineering from the University of South Carolina under Dr. Paul G. Huray.

Design for Signal and Power Integrity has made tremendous progress over the last three decades thanks mainly to the modeling and measurement methods developed and the knowledge base derived from it. Over the last several years the SI/PI community has been focusing on applying machine learning (ML) methods to speed-up computations and ease the design process. But how useful has ML been in the domain of signal and power integrity?
This presentation will cover several ML based approaches applied for SIPI design highlighting the insights gained and future directions in this area.

Madhavan Swaminathan is the Department Head of Electrical Engineering and is the William E. Leonhard Endowed Chair at Penn State University. He also serves as the Director for the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), an SRC JUMP 2.0 Center www.chimes.psu.edu.
Prior to joining Penn State, he was the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT). Prior to GT, he was with IBM working on packaging for supercomputers.
He is the author of 650+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is a Fellow of IEEE, Fellow of the National Academy of Inventors (NAI), Fellow of Asia-Pacific Artificial Intelligence Association (AAIA), and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He has been recognized through many awards with the most recent one being the 2024 IEEE Rao R. Tummala Electronics Packaging Award (technical field award) for contributions to semiconductor packaging and system integration technologies that improve the performance, efficiency, and capabilities of electronic systems.
He received his MS and PhD degrees in Electrical Engineering from Syracuse University, USA.

Signal and power integrity (SIPI) is one of the main design bottlenecks affecting system performance. As a result, SIPI analysis must also be a core components of electronic design automation (EDA) tools. However, in addition to being a design bottleneck, they also present significant challenges to simulation and design automation tools. In this presentation we focus on the difficulties of integrating interconnect models of varying levels of complexity in the framework of a SPICE like simulators. We present the fundamental reasons why this results in a simulation bottleneck, and some of the established and state of the art methods for addressing this problem.

Prof. Roni Khazaka received his Bachelor, Master, and Ph.D. degrees in Electrical Engineering from Carleton University, Ottawa, Canada in 1995, 1998, and 2002, respectively. In 2002, he joined the Department of Electrical and Computer Engineering at McGill University, Montreal, QC, Canada, where he currently is an Associate Professor in the department of Electrical and Computer Engineering, and Associate Dean, Academic Program, in the Faculty of Engineering. Prof. Khazaka is a senior member of the IEEE. In 2009, he was a Visiting Research Fellow with the University of Shizuoka, Shizuoka, Japan. In 2017, he was a Visiting Researcher with the Politecnico di Torino, Turin, Italy. He has authored over 100 journal and conference articles in the areas of signal and power integrity, model order reduction, macromodeling and high frequency circuit simulations. His current research interests include signal and power integrity, electronic design automation, numerical algorithms and techniques, the analysis and simulation of RF ICs, and high-speed interconnects and packages.

A Power Distribution Network (PDN) plays a crucial role in delivering stable voltage and minimizing noise in high-speed electronic circuits. Decoupling capacitors are essential components in a PDN, but their effectiveness is impacted by parasitic elements. Proper placement of decoupling capacitors is critical and depends on both the PCB stack-up and the target frequency. This session explores these fundamental concepts, providing guidelines for selecting and placing decoupling capacitors for optimal performance.

Chulsoon Hwang is an Associate Professor at Missouri S&T. Before joining Missouri S&T in 2015, he worked at Samsung Electronics. His research focuses on signal/power integrity, RF/digital integration (RF desensitization), and machine learning-driven hardware design. He has authored or co-authored over 150 papers and has been a co-recipient of more than 10 Best Paper and Best Student Paper Awards at conferences such as IEEE EMC+SIPI, AP-EMC, and DesignCon.

This technical talk explores advanced power generation and delivery strategies for data centers, emphasizing emerging techniques such as embedding, vertical power delivery, and Integrated Voltage Regulators (IVRs) implemented at the module, PCB, package, and die levels. The discussion begins by highlighting current trends and pressing challenges in powering AI/ML workloads, including ±400V DC distribution, extreme currents exceeding 1000A per power rail, and power densities surpassing 1A/mm². Practical design examples based on the Open Compute Project’s (OCP) Open Accelerator Module (OAM) and Universal Base Board (UBB) architectures illustrate these challenges and their potential solutions. Furthermore, the talk evaluates the benefits and complexities associated with embedding technology, chiplet integration, and multi-level IVRs. Primarily forward-looking, the presentation provides insightful perspectives to inform future advancements in data center power infrastructure.

Zhiping Yang is the CEO of PCB Automation Inc. (https://pcbauto.ai) and an adjunct professor at Missouri S&T EMC laboratory.  He worked in Waymo, Google, Apple, Cisco, and Nuova systems on automotive, consumer, and datacenter products. His research interests include signal integrity and power integrity methodology development for Die/Package/Board co-design, high-speed optical module, various high-speed cabling solutions, high-speed DRAM/storage technology, and high-speed serial signaling technology. He has published more than 70 research papers and 20 patents. His research and patents have been applied in Apple iPhone 5S/6/6S, Cisco UCS, Cisco Nexus 6K/4K/3K, and Cisco Cat6K products. He is actively involved with the IBIS Open Forum as a BoD member and officer. He is an IEEE Fellow and served the Technical Advisory Committee leadership roles in IEEE EMC society. He obtained his Ph.D. from University of Missouri-Rolla and his B.S. and M.S. from Tsinghua University, Beijing.

Modern high-speed electronic systems, particularly those employing advanced ASIC and chiplet packages for AI and data center applications, face critical challenges in managing power delivery network (PDN) integrity. High current densities, coupled with higher power rail density on the package and demanding data rates, contribute to significant challenges. While PDN impedance is a key metric, measuring high-current PDNs (e.g., 2000A) presents difficulties, notably ground loop errors in 2-port measurements. Employing ground loop isolators with adequate Common-Mode Rejection Ratio (CMRR) is crucial. This presentation will demonstrate a practical approach to accurately measure a 2000-Amp (or 40 µΩ) PDN using various VNAs. We will detail how to determine the minimum CMRR needed for reliable 2-port probe measurements and show that sub-40 µΩ impedance measurements are achievable with isolators possessing sufficient CMRR.

Benjamin Dannan is the Founder and Chief Technologist at Signal Edge Solutions. Benjamin Dannan is an experienced signal and power integrity (SI/PI) design consultant developing advanced packaging solutions for high-performance ASICs, chiplets, and complex FPGA designs. He is a Keysight ADS Certified Expert with expert-level proficiency in high-speed simulation solutions and multiple 3D EM solutions. He has expert-level proficiency with multiple test and measurement solutions, including oscilloscopes, vector network analyzers (VNA), Time Domain Reflectometers (TDRs), function generators, and EMC lab testing equipment.